1. Field of the Invention
This invention relates to a semiconductor fabrication, and more particularly to a method for forming a passivation layer formed over an interconnect metal layer whose planarity is improved by properly patterning the interconnect metal layer before forming the passivation layer.
2. Description of Related Art
In semiconductor fabrication, an integrated circuit (IC) device is formed over a semiconductor substrate. The IC device usually includes, for example, transistors and capacitors, which are interconnected by an interconnect metal layer. After the structure of the IC device is formed, a passivation layer then is formed over the IC structure so as to protect the IC device from external damages. In order to effectively protect the IC structure, the passivation layer must be uniformly deposited, have no voids and sufficient hardness, and be able to resist cracking, penetration of water vapor or alkaline ions, and mechanical damages.
Some common materials for forming the passivation layer include silicon nitride or phosphosilicate glass (PSG). The silicon nitride material has a high density and a great hardness so that silicon nitride can effectively resist the penetration of water vapor or alkaline ions and resist mechanical damages. The PSG material includes phosphoric atoms, which have a gettering property so that the water vapor and alkaline ions are effectively absorbed by it. The lifetime of the IC device thereby is prolonged.
FIGS. 1A-1D are cross-sectional views of a semiconductor device schematically illustrating a conventional fabrication process for forming a passivation layer over a semiconductor substrate.
In FIG. 1A, a metal layer 12 is formed over a semiconductor substrate 10. The substrate 10 includes a structure of an IC device, such as a metal-oxide semiconductor (MOS) transistor, a dielectric layer, and an interconnect metal layer with a proper couplings, all of which structures are not shown in the figure. The metal layer 12 includes aluminum or aluminum alloy. The metal layer 12 is the top interconnect metal layer in the IC device. A photoresist layer 14 with a desired pattern is formed over the metal layer 12.
In FIG. 1B, using the photoresist layer 14 as an etching mask, the metal layer 12 is patterned to form a metal layer 12a through an etching process such as dry etching. An opening 15 is thereby formed in the metal layer 12a to expose the substrate 10. The opening 15 on the side is wider and is not fully shown. The photoresist layer 14 of FIG. 1 is removed. The metal layer 12a has several sharp corners 13 on each side edge due to the formation of the opening 15. The sharp corners 13 affect the planarity of a passivation layer that is to be subsequently formed.
In FIG. 1C, a PSG layer 16 is formed over the substrate 10 through atmospheric chemical vapor deposition (APCVD) or low pressure chemical vapor deposition (LPCVD). The PSG layer 16 is conformal to the metal layer 12a. The PSG layer 16 servers as a first passivation layer to protect the IC device from penetration of water vapor or alkaline ions. Referring to FIG. 1B and FIG. 1C, when the PSG material is deposited over the substrate 10, the growing rate of the PSG layer 16 on the bottom of the opening 15 is less than the growing rate at the sharp corners 13, due to the structure of the sharp corners 13. A little overhang structure 17 occurs on the sharp corners 13. The step coverage over the opening 15 is not sufficient.
In FIG. 1D, a dielectric layer 18 is formed over the substrate 10. The dielectric layer 18 includes silicon nitride with high density and great hardness. The dielectric layer 18 serves as a second passivation layer to protect the IC device below the passivation layer. Due to the overhang structure 17 in the PSG layer 16, it is difficult to deposit the dielectric layer 18. The step coverage is worsened. A void 21 is formed in the dielectric layer 18 due to the large aspect ratio, in which the aspect ratio is defined as the ratio of the depth to the width of an opening. The dielectric layer 18 also has an acute angle structure 19 at the lower corner of the metal layer 12a within the wider side openings 15 shown in FIG. 1B. At the acute angle structure 19, a crack may easily occur. The formation of the acute angle structure 19 also results from the overhang structure 17 in the PSG layer 16, which causes a higher depositing rate on the upper outer corner of the metal layer 12a. The overhang phenomenon is worsened.
In conclusion, the conventional method for forming the passivation layer lacks sufficient planarity, and has a void in the opening and a crack at the acute angle structure 19.